The present invention relates to a semiconductor memory device, and more particularly relates to a static random access memory (SRAM).
With recent downsizing in semiconductor processing, variation in transistor characteristics has been increasing. This has a large effect on circuit yields, and designs for suppressing the variation in transistor characteristics will become more and more important.
An SRAM memory cell of a six-transistor CMOS type has been known to date. This SRAM memory cell is constituted by three types of transistors (six transistors) in total, i.e., a pair of NMOS access transistors, a pair of NMOS drive transistors and a pair of PMOS load transistors.
To suppress variation in manufacturing SRAM memory cells and to reduce the memory cell area and the bit-line capacitance, a planar cell structure was devised. Unlike a vertical cell structure having an N-well in the upper half of a memory cell region and a P-well in the lower half thereof, in the planar cell structure, a pair of PMOS load transistors is placed on an N-well located at the center of a memory cell region, a first NMOS access transistor and a first NMOS drive transistor are placed on a left-hand P-well, and a second NMOS access transistor and a second NMOS drive transistor are placed on a right-hand P-well. In this case, the direction in which a bit line runs is defined as a longitudinal direction and the direction in which a word line runs is defined as a lateral direction (See U.S. Pat. Nos. 5,744,844 and 5,930,163).
In the vertical cell structure, an access transistor and a drive transistor are laid out to have their respective gates disposed vertically to each other. On the other hand, in the planar cell structure, an access transistor and a drive transistor are laid out to have their respective gates disposed in parallel with each other, so that the structure is less affected by variation in manufacture. In addition, the amount of wasted space is smaller than in the vertical cell structure, so that the memory cell area decreases and the bit line length becomes shorter accordingly, resulting in a small capacitance.
A static noise margin in read operation is one of the measures of stability of the memory cell. The static noise margin indicates whether data held in the memory cell is destroyed or not when a word line is activated. As the static noise margin increases, the memory cell in read operation becomes more stable (see Japanese Laid-Open Publication No. 2002-042476).
Conventionally, to increase the static noise margin in read operation, the current drive capability of a drive transistor is made higher than that of an access transistor in a memory cell. Specifically, the gate-width ratio of the access transistor to the drive transistor is set at about 1:1.5, for example. A six-transistor memory cell includes a high-potential memory node and a low-potential memory node so that when a word line is activated for read operation, current flows from one of a pair of bit lines precharged to a power supply voltage into the low-potential memory node. Accordingly, the voltage at the low-potential memory node rises to a potential determined by the ratio between the on-state resistance of the access transistor and the on-state resistance of the drive transistor. If this voltage rise is too large, a malfunction that the data held in the low-potential memory node changes to high occurs. In view of this, to suppress such a voltage rise at the low-potential memory node in read operation, the current drive capability of the drive transistor is conventionally set high to have the on-state resistance of the drive transistor low.
If the planar cell structure is adopted for an SRAM and the gate width of an access transistor is smaller than that of a drive transistor as described above, a doped layer of the access transistor is bent in a concave shape at the gate thereof. During a process for fabricating such an SRAM memory cell, if the gate of the access transistor shifts along the channel direction of the transistors, the effective gate width of the access transistor increases, so that electrical characteristics of the transistor change greatly. As a result, there arise a problem that the static noise margin decreases to cause a malfunction in read operation and thus the yield decreases largely.